Title :
Noise analysis for digit slicing FFT
Author :
Sharrif, Z.A.M. ; Othman, M. ; Theong, T.S.
Author_Institution :
Dept. of Electr. Electron. & Syst. Eng., Nat. Univ. of Malaysia, Selangor, Malaysia
fDate :
10/1/1991 12:00:00 AM
Abstract :
The digit slicing architecture of the fast Fourier transform is modular in nature and easily applicable to VLSI implementation. The error caused by the digit slicing implementation of on chip fast Fourier transform is analysed. A mathematical model is proposed to arrive at the signal to noise ratio of a general sliced structure by modelling the error as an additive white noise. The model is capable of satisfactorily predicting the signal to noise ratio
Keywords :
fast Fourier transforms; white noise; SNR; VLSI; additive white noise; digit slicing FFT; digit slicing architecture; error; fast Fourier transform; mathematical model; noise analysis; noise model; signal to noise ratio;
Journal_Title :
Radar and Signal Processing, IEE Proceedings F
