Title :
Constraint transformation for IC physical design
Author :
Malavasi, Enrico ; Charbon, Edoardo
Author_Institution :
Cadence Design Syst. Inc., San Jose, CA, USA
fDate :
11/1/1999 12:00:00 AM
Abstract :
In a top-down design methodology, design tasks are divided into simpler subtasks across levels of a hierarchy as an effective divide-and-conquer technique. For every task, tolerances are defined on all performance characteristics to take into account parasitics, mismatches, and other nondeterministic process parameter variations. Constraint transformation is a process used to translate performance specifications into subtask requirements. This paper introduces the problem of constraint transformation and describes some formal solutions for analog circuit applications. Examples illustrate the methodology and show the suitability of this approach in industrial-strength applications
Keywords :
constraint theory; divide and conquer methods; integrated circuit design; tolerance analysis; IC physical design; analog circuit; constraint transformation; divide-and-conquer technique; nondeterministic process; sensitivity; tolerance aware model; top-down design; Analog circuits; Design methodology; Fabrication; Helium; Integrated circuit reliability; Power system modeling; Process design; Robustness; Stress; Time to market;
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
