Title :
Logical clock requirements for reverse engineering scenarios from a distributed system
Author :
Hrischuk, Curtis E. ; Woodside, C. Murry
Author_Institution :
Rational Software, Woodinville, WA, USA
fDate :
4/1/2002 12:00:00 AM
Abstract :
To reverse engineer scenarios from event traces, one must infer causal relationships between events. The inferences are usually based on a trace with sequence numbers or timestamps corresponding to some kind of logical clock. In practice, there is an explosion of potentially causal relationships in the trace, which limits one\´s ability to extract scenarios. This work defines a more parsimonious form of causality called scenario causality that concentrates on certain major causal relationships and ignores more subtle, potentially causal links. The influence of an event is restricted to the particular scenario it is part of. An event which is not a message reception is defined to be caused by the previous event in the same software object, while a message reception is caused by a sending event in another object. The events are ordered to form a scenario event graph where typed nodes are events and the typed edges are certain causal relationships. Intuitively, we might say that most logical clocks, which identify events which "happened before" a given event and, thus, are potentially causal, give an upper bound on the set of causal events; scenario causality identifies a lower bound. The much smaller lower bound set makes it possible to reverse engineer and automate the analysis of scenarios
Keywords :
causality; clocks; distributed programming; graph grammars; program debugging; program diagnostics; reverse engineering; software engineering; World Wide Web services; automatic scenario analysis; causal order; causal relationship inference; debugging; distributed programming; distributed system; event labeling; event traces; graph grammar; logical clock requirements; lower bound; message reception; parsimonious causality; scenario causality; scenario event graph; scenario reverse engineering; sending event; software objects; software tracing; timestamps; trace analysis; trace sequence numbers; typed edges; typed nodes; upper bound; Clocks; Reverse engineering;
Journal_Title :
Software Engineering, IEEE Transactions on
DOI :
10.1109/TSE.2002.995416