Built-in test sequence generation for synchronous sequential circuits based on loading and expansion of input sequences using single and multiple fault detection times

We describe an on-chip test generation scheme for synchronous sequential circuits that allows at-speed testing of such circuits. The proposed scheme is based on loading of (short) input sequences into an on-chip memory and expansion of these sequences on-chip into test sequences. Complete coverage of modeled faults is achieved by basing the selection of the loaded sequences on a deterministic test sequence T₀ and ensuring that every fault detected by T₀ is detected by the expanded version of at least one loaded sequence. Specifically, each input sequence S is constructed based on a different fault f and is extracted from T₀ around a time unit where f is detected by T₀. Experimental results presented for benchmark circuits show that the length of the sequence that needs to be stored on-chip at any given time is, on the average, 11 percent of the length of T₀ and that the total length of all the loaded sequences is, on the average, 48 percent of the length of T₀. These results are obtained by extracting each sequence S around the first detection time of a target fault f. These results are further improved by considering several time units for every target fault f and selecting the shortest possible sequence based on f