DocumentCode :
1272061
Title :
A versatile time-domain Reed-Solomon decoder
Author :
Shayan, Yousef R. ; Le-Ngoc, Tho ; Bhargava, Vijay K.
Author_Institution :
SR Telecom Inc., St. Laurent, Que., Canada
Volume :
8
Issue :
8
fYear :
1990
fDate :
10/1/1990 12:00:00 AM
Firstpage :
1535
Lastpage :
1542
Abstract :
A versatile Reed-Solomon (RS) decoder structure based on the time-domain decoding algorithm (transform decoding without transforms) is developed. The algorithm is restructured, and a method is given to decode any RS code generated by any generator polynomial. The main advantage of the decoder structure is its versatility, that is, it can be programmed to decode any Reed-Solomon code defined in Galois field (GF) 2m with a fixed symbol size m. This decoder can correct errors and erasures for any RS code, including shortened and singly extended codes. It is shown that the decoder has a very simple structure and can be used to design high-speed single-chip VLSI decoders. As an example, a gate-array-based programmable RS decoder is implemented on a single chip. This decoder chip can decode any RS code defined in GF (25) with any code word length and any number of information symbols. The decoder chip is fabricated using low-power 1.5-μ, two-layer-metal, HCMOS technology
Keywords :
CMOS integrated circuits; VLSI; decoding; error correction codes; logic arrays; time-domain synthesis; 1.5 micron; Galois field; VLSI gate-array-based decoder; time-domain Reed-Solomon decoder; two-layer-metal HCMOS; Data storage systems; Decoding; Error correction codes; Galois fields; Hardware; Reed-Solomon codes; Strontium; Telecommunication computing; Time domain analysis; Very large scale integration;
fLanguage :
English
Journal_Title :
Selected Areas in Communications, IEEE Journal on
Publisher :
ieee
ISSN :
0733-8716
Type :
jour
DOI :
10.1109/49.62831
Filename :
62831
Link To Document :
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