• DocumentCode
    1272131
  • Title

    Efficient VLSI layouts for homogeneous product networks

  • Author

    Fernández, Antonio ; Efe, Kemal

  • Author_Institution
    Dept. de Arquitectura, Escuela Univ. de Inf., Madrid, Spain
  • Volume
    46
  • Issue
    10
  • fYear
    1997
  • fDate
    10/1/1997 12:00:00 AM
  • Firstpage
    1070
  • Lastpage
    1082
  • Abstract
    In this paper, we develop generalized methods to layout homogeneous product networks with any number of dimensions, and analyze their VLSI complexity by deriving upper and lower bounds on the area and maximum wire length. In the literature, lower bounds are generally obtained by computing lower bounds on the bisection width or the crossing number of the network being laid out. In this paper, we define a new measure that we call “maximal congestion”, that can be used to obtain both the bisection width and the crossing number, thereby unifying the two approaches. Upper bounds are traditionally obtained by constructing layouts based on separators or bifurcators. Both methods have the basic limitation that they are applicable only for graphs with bounded vertex degree. The separators approach generally yields good layouts when good separators can be found, but it is difficult to find a good separator for an arbitrary graph. The bifurcators approach is easier to apply, but it generally yields larger area and wire lengths. We show how to obtain “strong separators” as well as bifurcators for any homogeneous product network, as long as the factor graph has bounded vertex degree. We illustrate application of both methods to layout a number of interesting product networks. Furthermore, we introduce a new layout method for product networks based on the combination of collinear layouts. This method is more powerful than the two methods above because it is applicable even when the factor graph has unbounded vertex degree. It also yields smaller area than the earlier methods. In fact, our method has led to the optimal area for all of the homogeneous product networks we considered in this paper with one exception, which is very close to optimal. In regards to wire lengths, the results obtained by our method turned out to be the best of the three methods for all the examples we considered, again subject to one (and the same) exception. We give an extensive variety of such examples
  • Keywords
    VLSI; circuit layout CAD; computational complexity; multiprocessor interconnection networks; VLSI complexity; VLSI layouts; bifurcators; bifurcators approach; factor graph; homogeneous product networks; lower bounds; maximal congestion; upper bounds; Bifurcation; Computer networks; Hypercubes; Multiprocessor interconnection networks; Particle separators; Partitioning algorithms; Routing; Upper bound; Very large scale integration; Wire;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/12.628392
  • Filename
    628392