Abstract :
Scaling complementary metal oxide semiconductor (CMOS) devices has been a method used very successfully over the last four decades to improve the performance and the functionality of very large scale integrated (VLSI) designs. Still, scaling is heading towards several fundamental limits as the feature size is being decreased towards 10 nm and less. One of the challenges associated with scaling is the expected increase of static and dynamic parameter fluctuations and variations, as well as intrinsic and extrinsic noises, with significant effects on reliability. Therefore, there is a clear, growing need for electronic design automation (EDA) tools that can predict the reliability of future massive nano-scaled designs with very high accuracy. Such tools are essential to help VLSI designers optimize the conflicting tradeoffs between area-power-delay and reliability requirements. In this paper, we introduce an EDA tool that quickly and accurately estimates the reliability of any CMOS gate. The tool improves the accuracy of the reliability calculation at the gate level by taking into consideration the gate´s topology, the reliability of the individual devices, the applied input vector, as well as the noise margins. It can also be used to estimate the effect on different types of faults and defects, and to estimate the effects of enhancing the reliability of individual devices on the gate´s overall reliability.
Keywords :
Bayes methods; CMOS integrated circuits; VLSI; electronic design automation; semiconductor device reliability; Bayesian networks; CMOS gate; EDA tool; VLSI design; complementary metal oxide semiconductor gates; electronic design automation tools; massive nanoscaled design; noise margins; reliability; very large scale integrated designs; CMOS integrated circuits; Integrated circuit reliability; Logic gates; Reliability engineering; Threshold voltage; Transistors; Bayesian network; CMOS transistors; design automation; digital circuit; nanotechnology; reliability modeling;
