Title :
A single chip motion JPEG codec LSI
Author :
Okada, S. ; Matsuda, Y. ; Watanabe, T. ; Kondo, K.
Author_Institution :
Microelectron. Res. Center, Sanyo Electr. Co. Ltd., Gifu, Japan
fDate :
8/1/1997 12:00:00 AM
Abstract :
We have developed a single chip motion JPEG codec LSI that can compress and decompress VGA-size (640 pixels×480 lines) JPEG images at the rate of 30 frames per second simply by connecting a single external buffer memory chip. The LSI can control compression ratio control technique to store a fixed number of images when there is limited memory capacity, and it compresses data stored in the frame buffer to enable high-speed signal processing without the use of high-speed image memory. The JPEG codec core is small (40000 gates) and power consumption is low (220 mW), making it well suited to a wide range of image processing applications in consumer products
Keywords :
buffer storage; code standards; consumer electronics; data compression; decoding; digital signal processing chips; integrated memory circuits; large scale integration; telecommunication standards; video codecs; video coding; 220 mW; LSI; VGA size JPEG images; compression ratio control; consumer products; data compression; external buffer memory chip; frame buffer; high-speed signal processing; image compression; image decompression; image processing applications; memory capacity; power consumption; single chip motion JPEG codec; Buffer storage; Codecs; Energy consumption; Image coding; Image processing; Joining processes; Large scale integration; Pixel; Signal processing; Transform coding;
Journal_Title :
Consumer Electronics, IEEE Transactions on
