A bus-monitoring model for MPEG video decoder design

Author

Ling, Nam ; Li, Jui-Hua

Author_Institution

Dept. of Comput. Eng., Santa Clara Univ., CA, USA

Volume

43

Issue

3

fYear

1997

fDate

8/1/1997 12:00:00 AM

Firstpage

526

Lastpage

530

Abstract

The variety of macroblock types and variable-length codes has increased the difficulty in predicting memory accesses and bus utilization pattern for accessing compressed data or pixels to/from external RAMs during the MPEG video decoding process. In this paper, we present a model and a simulator to aid MPEG decoder design by providing useful statistics related to bus utilization and waiting cycles. The model explores MPEG decoder architecture and data nature; it provides results to analyze bus bandwidth and determine proper sizes of decoder I/O buffers connected to the bus. Simulation is performed to test out different bus arbitration schemes for MP@ML data in MPEG-2 decoding

Keywords

buffer storage; decoding; digital simulation; monitoring; simulation; system buses; variable length codes; video equipment; video signal processing; I/O buffers; MPEG video decoder design; bus arbitration schemes; bus bandwidth; bus utilization pattern; bus-monitoring model; compressed data; data nature; decoder architecture; decoder design; external RAM; macroblock types; memory accesses; statistics; variable-length codes; waiting cycle; Bandwidth; Data engineering; Decoding; Displays; Motion compensation; Random access memory; Read-write memory; Solid modeling; Transform coding; Video compression;

fLanguage

English

Journal_Title

Consumer Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0098-3063

Type

jour

DOI

10.1109/30.628670

Filename

628670