A high speed VLSI architecture of discrete wavelet transform for MPEG-4

We present a high speed VLSI architecture of the discrete wavelet transform (DWT) for MPEG-4. We found similarities between the computation results of each octave. By using the similarities, in the proposed architecture, the input data are separated between even and odd, and the two data streams are inputted in parallel. This causes faster discrete wavelet transform operation than other architectures. In conventional architectures, the N-point DWT is computed in N cycles or 2N cycles. Whereas, in the proposed architecture the N-point DWT is computed in N/2 cycles with 100% hardware utilization. Therefore, the proposed architecture can be applied in the MPEG-4 standard, image transmission in wireless networks and digital signal processing which require high speed processing