Title :
An HDTV video coder IC for ATV receivers
Author :
Duardo, Obed ; Hsieh, Shining ; Wu, Les ; Boo, Jonathan ; Khurjekar, Aditya ; Hingorani, Rajesh ; Wilford, Paul ; Bolton, Brad ; Morinaka, Hiroyuki ; Okada, Keisuke ; Hosotani, Shiro ; Sumi, Tadashi ; DaGraca, Paul ; Yamamoto, Hiroshi ; Poon, Tommy
Author_Institution :
Lucent Technol., Bell Labs., Murray Hill, NJ, USA
fDate :
8/1/1997 12:00:00 AM
Abstract :
An HDTV video decoder IC for ATV receivers is presented. Its dual decoder architecture supports MPEG-2 MP@HL (62,668,800 display samples per second) and an SDRAM memory bandwidth of 6.5 gigabits per second
Keywords :
CMOS digital integrated circuits; DRAM chips; code standards; decoding; digital signal processing chips; high definition television; television receivers; video coding; 6.5 Gbit/s; ATV receivers; CMOS; HDTV video coder IC; MPEG-2 MP@HL; SDRAM memory bandwidth; dual decoder architecture; Bandwidth; Costs; Decoding; Displays; HDTV; SDRAM; TV; Throughput; Transform coding; Video compression;
Journal_Title :
Consumer Electronics, IEEE Transactions on
