Design of an image edge detection filter using the Sobel operator

Author

Kanopoulos, N. ; Vasanthavada, N. ; Baker, Robert L.

Author_Institution

Research Triangle Inst., Research Triangle Park, NC, USA

Volume

23

Issue

2

fYear

1988

fDate

4/1/1988 12:00:00 AM

Firstpage

358

Lastpage

367

Abstract

The architecture of the edge detector presented is highly pipeline to perform the computations of gradient magnitude and direction for the output image samples. The chip design is based on a 2-μm, double-metal, CMOS technology and was implemented using a silicon compiler system in less than 2 man-months. It is designed to operate with a 10-MHz two-phase clock, and it performs approximately 200×10⁶ additions/s to provide the required magnitude and direction outputs every clock cycle. The function of the chip has been demonstrated with a prototype system that is performing image edge detection in real time

Keywords

CMOS integrated circuits; VLSI; computerised pattern recognition; computerised picture processing; digital filters; 10 MHz; 2 micron; 200×10⁶ additions/s; ASIC; CMOS technology; Sobel operator; VLSI; chip design; clock 10 MHz; custom IC; double-metal; edge detector; image edge detection filter; image edge detection in real time; prototype system; silicon compiler system; two-phase clock; CMOS technology; Chip scale packaging; Clocks; Computer architecture; Detectors; Filters; High performance computing; Image edge detection; Pipelines; Silicon compiler;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.996

Filename

996