Through-Strata-Via (TSV) Parasitics and Wideband Modeling for Three-Dimensional Integration/Packaging

Author

Xu, Zheng ; Lu, Jian-Qiang

Author_Institution

Dept. of Electr., Comput., & Syst. Eng., Rensselaer Polytech. Inst., Troy, NY, USA

Volume

32

Issue

9

fYear

2011

Firstpage

1278

Lastpage

1280

Abstract

This letter reports on techniques of full-wave extractions and analytical calculations to investigate the through-strata-via (TSV) parasitics in 3-D integration/packaging. Both methods suggest close TSV RLGC results over the entire frequency range of interest. A wideband SPICE model is generated from the TSV electromagnetic solutions with good agreement for both magnitudes and phases of return loss and insertion loss. Further sensitivity analysis results indicate that the isolation layer thickness weighs most in the signal gain at 20 GHz. This letter provides some insight to TSV electrical characteristics and helps TSV physical design to maximize the benefits of 3-D systems.

Keywords

SPICE; integrated circuit packaging; isolation technology; sensitivity analysis; three-dimensional integrated circuits; 3D packaging; TSV RLGC; TSV electrical characteristics; TSV electromagnetic solution; TSV parasitics; TSV physical design; full-wave extraction techniques; insertion loss; isolation layer; return loss; sensitivity analysis; three-dimensional integration; through-strata-via parasitics; wideband SPICE model; Copper; Integrated circuit modeling; Packaging; SPICE; Solid modeling; Three dimensional displays; Through-silicon vias; 3-D integration; Modeling; RLGC extraction; packaging; sensitivity analysis; through-strata-via (TSV);

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2011.2158511

Filename

5954151