Title :
Development of a digital FPLL ASIC for GA HDTV receivers
Author :
Han, Dong-Seog ; Lee, Myeong-Hwan ; Park, Kil-Houm
Author_Institution :
Dept. of Electron. & Electr. Eng., Kyungpook Nat. Univ., Taegu, South Korea
fDate :
8/1/1997 12:00:00 AM
Abstract :
We propose a new digital carrier recovery loop architecture for the Grand Alliance high definition television (HDTV) system. We have developed an application specific integrated circuit (ASIC) based on the new architecture. The developed ASIC has a gate count of 60 K with a gate array technology that features 0.5 μm, 3.3 V and 2-metal-layer technology. The pull-in range of the proposed architecture is about ±250 kHz with 0 dB carrier-to-noise ratio (CNR)
Keywords :
CMOS logic circuits; application specific integrated circuits; digital phase locked loops; digital signal processing chips; digital television; high definition television; logic arrays; television receivers; 0.5 micron; 2-metal-layer technology; 3.3 V; GA HDTV receivers; Grand Alliance; HDTV system; application specific integrated circuit; carrier to noise ratio; digital FPLL ASIC; digital TV standard; digital carrier recovery loop architecture; frequency/phase locked loop; gate array technology; gate count; high definition television; pull-in range; Amplitude modulation; Application specific integrated circuits; Demodulation; Digital filters; Digital modulation; Frequency; HDTV; Integrated circuit technology; Quadrature amplitude modulation; TV;
Journal_Title :
Consumer Electronics, IEEE Transactions on
