Title :
FPGA based runtime configurable clause evaluator for SAT problems
Author :
Leong, P.H.W. ; Chung, C.K.
Author_Institution :
Dept. of Comput. Sci. & Eng., Chinese Univ. of Hong Kong, Shatin, Hong Kong
fDate :
9/16/1999 12:00:00 AM
Abstract :
An FPGA based clause evaluator for Boolean satisfiability problems is presented in which a customised bitstream is directly generated from the problem specification, avoiding the need for resynthesis. A three orders of magnitude improvement in reconfiguration time was seen over the standard approach for a 50 variable, 80 clause problem
Keywords :
Boolean functions; constraint theory; field programmable gate arrays; logic CAD; Boolean satisfiability problems; FPGA based clause evaluator; SAT problems; customised bitstream; runtime configurable clause evaluator;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19991132
