5 Gbit/s 2:1 multiplexer fabricated in 0.35 μm CMOS and 3 Gbit/s 1:2 demultiplexer fabricated in 0.5 μm CMOS technology

The 5 Gbit/s 2:1 multiplexer is fabricated in 0.35 μm CMOS and the 3 Gbit/s 1:2 demultiplexer is fabricated in 0.5 μm CMOS technology The authors have designed two dynamic CMOS circuits (based on dynamic transmission gate logic), a 5 Gbit/s 2:1 multiplexer and a 3 Gbit/s 1:2 demultiplexer, which can be used in the place of their counterpart CML circuits. Both circuits feature front-end amplification to convert CML levels to CMOS logic swings, and open drain output drivers with CML levels into 50 Ω