Efficient FPGA implementation of a high-quality super-resolution algorithm with real-time performance

Nowadays, most of the image contents are recorded in high resolution (HR). Nevertheless, there is still a need of low resolution (LR) content presentation when recapturing is unviable. As high resolution content becomes commonplace (with HDTV penetration in US estimated at 65% for 2010) the viewers expectations on quality and presentation become higher and higher. Thus, in order to meet today¿s consumer expectations the LR content quality has to be enhanced before being displayed. Content pre-processing/upscaling methods include interpolation and Super-Resolution Image Reconstruction (SRIR). SRIR hardware implementations are scarce, mainly due to high memory and performance requirements. This is the challenge we address. In this work an efficient super-resolution core implementation with high quality of the super-resolved outcome is presented. In order to provide high outcome quality the implementation is based on state-of-the-art software. The software algorithm is presented and its output quality compared with other state-of-the-art solutions. The results of the comparison show that the software provides superior output quality. When implemented in targeted FPGA device, the system operating frequency was estimated at 109 MHz. This resulted in a performance that allows dynamic 2x super resolution of QCIF YUV 4:2:0p sequences at a frame rate of 25 fps, leading to realtime execution using only on-chip device memory. Post-layout simulations with back-annotated time proved that the hardware implementation is capable of producing the same output quality as the base software.