Title :
Design and implementation of MPEG-2/DVB scrambler unit and VLSI chip
Author :
Kim, Won-Ho ; Chen, Kyung-Jae ; Cho, Hyun-Suk
Author_Institution :
Satellite Commun. Div., ETRI, Taejon, South Korea
fDate :
8/1/1997 12:00:00 AM
Abstract :
This paper describes the MPEG-2/DVB scrambler unit (DVB-SU) and VLSI chip developed for ETRI´s conditional access system (CAS) for a digital broadcasting system. The DVB-SU is designed and implemented based on an ASIC, FPGAs and a DSP. The ASIC, compliant with the EP-DVB common scrambling specification, is a 128-pin MQFP type and operates with a 50 MHz system clock; it has features of flexible conditional access handling and interfaces with a commercial MPEG-2 multiplexer in compliance with the MPEG-2 system specification (ISO/IEC 13818). It has been integrated as a part of a conditional access sub-system for a digital broadcasting system and conforms so that it meets all the initial objectives and performance requirements
Keywords :
CMOS digital integrated circuits; ISO standards; VLSI; application specific integrated circuits; cryptography; digital signal processing chips; digital television; direct broadcasting by satellite; telecommunication standards; television broadcasting; television receivers; television standards; 128-pin MQFP type ASIC; 50 MHz; DBS; DSP; DVB-SU; EP-DVB common scrambling specification; ETRI conditional access system; FPGA; ISO/IEC 13818; MPEG-2 multiplexer; MPEG-2 system specification; MPEG-2/DVB scrambler unit; VLSI chip; conditional access sub-system; digital video broadcasting; flexible conditional access handling; Application specific integrated circuits; Clocks; Content addressable storage; Digital signal processing chips; Digital video broadcasting; Field programmable gate arrays; IEC standards; ISO standards; Multiplexing; Very large scale integration;
Journal_Title :
Consumer Electronics, IEEE Transactions on
