DocumentCode :
1275400
Title :
An analytical model on the blocking probability of a fault-tolerant network
Author :
Haynos, Mathew P. ; Yang, Yuanyuan
Author_Institution :
IBM Corp., Encinitas, CA, USA
Volume :
10
Issue :
10
fYear :
1999
fDate :
10/1/1999 12:00:00 AM
Firstpage :
1040
Lastpage :
1051
Abstract :
The well-known Clos network has been extensively used for telephone switching, multiprocessor interconnection and data communications. Much work has been done to develop analytical models for understanding the routing blocking probability of the Clos network. However, none of the analytical models for estimating the blocking probability of this type of network have taken into account the very real possibility of the interstage links in the network failing. In this paper, we consider the routing between arbitrary network inputs and outputs in the Clos network in the presence of interstage link faults. In particular, we present an analytical model for the routing blocking probability of the Clos network which incorporates the probability of interstage link failure to allow for a more realistic and useful determination of the approximation of blocking probability. We also conduct extensive simulations to validate the model. Our analytical and simulation results demonstrate that for a relatively small interstage link failure probability, the blocking behavior of the Clos network is similar to that of a fault-free network, and indicate that the Clos network has a good fault-tolerant capability. The new integrated analytical model can guide network designers in the determination of the effects of network failure on the overall connecting capability of the network and allows for the examination of the relationship between network utilization and network failure
Keywords :
fault tolerant computing; multiprocessor interconnection networks; performance evaluation; telecommunication network routing; Clos network; analytical model; blocking behavior; blocking probability; data communications; fault-free network; fault-tolerant capability; fault-tolerant network; integrated analytical model; interstage link faults; multiprocessor interconnection; network failure; network utilization; simulation results; telephone switching; Analytical models; Computer architecture; Computer networks; Data communication; Fault tolerance; Joining processes; Multiprocessor interconnection networks; Routing; Switches; Telephony;
fLanguage :
English
Journal_Title :
Parallel and Distributed Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1045-9219
Type :
jour
DOI :
10.1109/71.808147
Filename :
808147
Link To Document :
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