Title :
A testbed for evaluation of fault-tolerant routing in multiprocessor interconnection networks
Author :
Vaidya, Aniruddha S. ; Das, Chita R. ; Sivasubramaniam, Anand
Author_Institution :
Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
fDate :
10/1/1999 12:00:00 AM
Abstract :
This paper presents a comprehensive evaluation testbed for interconnection networks and routing algorithms using real applications. The testbed is flexible enough to implement any network topology and fault-tolerant routing algorithm, and allows the system architect to study the cost versus performance trade-offs for a range of network parameters. We illustrate its use with one fault-tolerant algorithm and analyze the performance of four shared memory applications with different fault conditions. We also show how the testbed can be used to drive future research in fault-tolerant routing algorithms and architectures by proposing and evaluating novel architectural enhancements to the network router, called path selection heuristics (PSH). We propose three such schemes and the Least Recently Used (LRU) PSH is shown to give the best performance in the presence of faults
Keywords :
digital simulation; fault tolerant computing; multiprocessor interconnection networks; performance evaluation; telecommunication network routing; fault-tolerant algorithm; fault-tolerant routing; multiprocessor interconnection networks; network topology; path selection heuristics; performance trade-offs; testbed; Costs; Fault tolerance; Fault tolerant systems; Hardware; Intelligent networks; Multiprocessor interconnection networks; Network topology; Performance analysis; Routing; System testing;
Journal_Title :
Parallel and Distributed Systems, IEEE Transactions on