Title :
Hitting Time Analysis for Fault-Tolerant Communication at Nanoscale in Future Multiprocessor Platforms
Author :
Bogdan, Paul ; Marculescu, Radu
Author_Institution :
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
Abstract :
This paper investigates the on-chip stochastic communication and proposes an analytical model for computing its mean hitting time. Toward this end, we model the on-chip stochastic communication of any source-destination pair as a branching and annihilating random walk taking place on a finite mesh. The evolution of this branching process is studied via a master equation which helps us estimate the mean number of communication rounds needed to reach a destination node from a particular source node. Besides the probabilistic performance analysis, we also present experimental results for two concrete platforms and assess the potential of stochastic communication for future nanotechnologies.
Keywords :
fault tolerant computing; graph theory; multiprocessing systems; multiprocessor interconnection networks; network-on-chip; random processes; stochastic processes; annihilating random walk; branching process evolution; branching random walk; communication rounds; finite graph; hitting time analysis; multiprocessor platform; nanoscale fault-tolerant communication; nanotechnology; network-on-chip; on-chip stochastic communication; probabilistic performance analysis; source-destination pair; Differential equations; Equations; Markov processes; Protocols; Routing; System-on-a-chip; Energy; hitting time; network-on-chip (NoC); random walk; reliable communication;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2011.2138430
