Title :
The design of a fully integrated graphics system
Author :
Torrance, R.R. ; Sadler, S.P. ; Lamoureux, J.P. ; Lamarche, Jean ; Frank, David J. ; Leveille, Francois
Author_Institution :
Silicart Inc., Vaudreuil, Que., Canada
fDate :
4/1/1988 12:00:00 AM
Abstract :
The architecture and design of a CMOS chip implementing a medium-resolution graphics system are described. The chip, requiring no external support logic, outputs analog RGB signals at a 40-MHz pixel rate and directly controls a bit-map video RAM (VRAM) memory array. Scan rates and display formats are completely programmable. Pixels stored in the 1 K×1 K bit map can be any of 16 colors taken from a 4096-color palette. The chip can be directly interfaced to most common microprocessors. A 6.7-MIPS (million-instruction-per-second) internal reduced instruction set computer (RISC) CPU directly implements high-level graphics commands. The chip achieves a maximum draw speed of 10 million pixels/s. Designed in a Lisp machine environment, the 100000-transistor chip is implemented in 1.8-μm CMOS and contains standard cells, RAM, ROM, a color table, and three four-bit current-steered digital-to-analog converters (DACs)
Keywords :
CMOS integrated circuits; VLSI; computer graphic equipment; microprocessor chips; 1 Mbit; 1.8 micron; 4 bit; 40 MHz; 4096-color palette; 6.7 MIPS; ASIC; CMOS chip; DACs; Lisp machine environment; RAM; RGB signals; RISC; ROM; VLSI; VRAM; bit-map video RAM; color table; custom IC; digital-to-analog converters; display formats; draw speed of 10 million pixels/s; fully integrated graphics system; high-level graphics commands; medium-resolution graphics system; pixel rate; reduced instruction set computer; standard cells; CMOS logic circuits; Color; Computer aided instruction; Computer displays; Graphics; Logic arrays; Microprocessors; Programmable logic arrays; Random access memory; Read-write memory;
Journal_Title :
Solid-State Circuits, IEEE Journal of
