A system LSI memory redundancy technique using an ie-flash (inverse-gate-electrode flash) programming circuit

Author

Yamaoka, Masanao ; Yanagisawa, Kazumasa ; Shukuri, Shoji ; Norisue, Katsuhiro ; Ishibashi, Koichiro

Author_Institution

Central Res. Lab., Hitachi Ltd., Kokubunji, Japan

Volume

37

Issue

5

fYear

2002

fDate

5/1/2002 12:00:00 AM

Firstpage

599

Lastpage

604

Abstract

A new memory redundancy technique using inverse-gate-electrode flash (ie-flash) memory cells has been developed. The ie-flash can be fabricated by the conventional logic CMOS process, so no additional processes are necessary in using it in system LSIs, and it can be programmed by logic testers. We enhanced the reliability of ie-flash by using some circuits, increasing reliability to endure practical use. This new redundancy technique was successfully implemented in the cache memories of a 32-b RISC microprocessor

Keywords

CMOS digital integrated circuits; cache storage; flash memories; integrated circuit reliability; large scale integration; microprocessor chips; redundancy; 32 bit; CMOS process; RISC microprocessor; cache memories; ie-flash programming circuit; inverse-gate-electrode flash; logic testers; memory redundancy technique; reliability; system LSI; CMOS logic circuits; CMOS process; Cache memory; Circuit testing; Large scale integration; Logic testing; Microprocessors; Reduced instruction set computing; Redundancy; System testing;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.997853

Filename

997853