DocumentCode :
1276393
Title :
A 130-nm 6-GHz 256 × 32 bit leakage-tolerant register file
Author :
Krishnamurthy, Ram K. ; Alvandpour, Atila ; Balamurugan, Ganesh ; Shanbhag, Naresh R. ; Soumyanath, K. ; Borkar, Shekhar Y.
Author_Institution :
Microprocessor Res. Labs., Intel Corp., Hillsboro, OR, USA
Volume :
37
Issue :
5
fYear :
2002
fDate :
5/1/2002 12:00:00 AM
Firstpage :
624
Lastpage :
632
Abstract :
Describes a 256-word × 32-bit 4-read, 4-write ported register file for 6-GHz operation in 1.2-V 130-nm technology. The local bitline uses a pseudostatic technique for aggressive bitline active leakage reduction/tolerance to enable 16 bitcells/bitline, low-Vt usage, and 50% keeper downsizing. Gate-source underdrive of -V cc on read-select transistors is established without additional supply/bias voltages or gate-oxide overstress. 8% faster read performance and 36% higher dc noise robustness is achieved compared to dual-Vt bitline scheme optimized for high performance. Device-level measurements in the 130-nm technology show 703× bitline active leakage reduction, enabling continued Vt scaling and robust bitline scalability beyond 130-nm generation. Sustained performance and robustness benefit of the pseudostatic technique against conventional dynamic bitline with keeper-upsizing is also presented
Keywords :
CMOS digital integrated circuits; integrated circuit measurement; leakage currents; microprocessor chips; semiconductor storage; shift registers; 1.2 V; 130 nm; 32 bit; 6 GHz; aggressive bitline active leakage reduction/tolerance; bitline active leakage reduction; dc noise robustness; device-level measurements; gate-oxide overstress; gate-source underdrive; keeper downsizing; leakage-tolerant register file; local bitline; microprocessors; performance-critical memory components; ported register file; pseudostatic technique; read-select transistors; robust bitline scalability; supply/bias voltages; Active noise reduction; CMOS technology; Circuit noise; Clocks; Dynamic voltage scaling; Microprocessors; Noise robustness; Registers; Threshold voltage; Voltage control;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/4.997856
Filename :
997856
Link To Document :
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