A sub-130-nm conditional keeper technique

Author

Alvandpour, Atila ; Krishnamurthy, Ram K. ; Soumyanath, K. ; Borkar, Shekhar Y.

Author_Institution

Microprocessor Res. Labs., Intel Corp., Hillsboro, OR, USA

Volume

37

Issue

5

fYear

2002

fDate

5/1/2002 12:00:00 AM

Firstpage

633

Lastpage

638

Abstract

Increasing leakage currents combined with reduced noise margins significantly degrade the robustness of wide dynamic circuits. In this paper, we describe two conditional keeper topologies for improving the robustness of sub-130-nm wide dynamic circuits. They are applicable in normal mode of operation as well as during burn-in test. A large fraction of the keepers is activated conditionally, allowing the use of strong keepers with leaky precharged circuits without significant impact on performance of the circuits. Compared to conventional techniques, up to 28% higher performance has been observed for wide dynamic gates in a 130-nm technology. In addition, the proposed burn-in keeper results in 64% active area reduction

Keywords

VLSI; integrated circuit design; integrated circuit noise; integrated circuit reliability; leakage currents; logic gates; microprocessor chips; multiplexing; 130 nm; VLSI; burn-in test; conditional keeper technique; dynamic gates; leakage currents; leaky precharged circuits; microprocessors; noise margins; wide dynamic circuits; Circuit noise; Circuit testing; Circuit topology; Degradation; Delay; Leakage current; Microprocessors; Noise level; Noise reduction; Noise robustness;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.997857

Filename

997857