Title :
A low-swing clock double-edge triggered flip-flop
Author :
Kim, Chulwoo ; Kang, Sung-Mo
fDate :
5/1/2002 12:00:00 AM
Abstract :
A low-swing clock double-edge triggered flip-flop (LSDFF) is developed to reduce power consumption significantly compared to conventional flip-flops. The LSDFF avoids unnecessary internal node transitions to reduce power consumption. In addition, power consumption in the clock tree is reduced because LSDFF uses a double-edge triggered operation as well as a low-swing clock. To prevent performance degradation of the LSDFF due to low-swing clock, low-Vt transistors are used for the clocked transistors without significant leakage current problems. The power saving in flip-flop operation is estimated to be 28.6% to 49.6% with additional 78% power saving in the clock network
Keywords :
VLSI; clocks; flip-flops; leakage currents; low-power electronics; VLSI; clock network; clock tree; double-edge triggered flip-flop; internal node transitions; leakage current; low-swing clock; performance degradation; power consumption; power saving; Capacitance; Clocks; Degradation; Energy consumption; Flip-flops; Leakage current; MOSFETs; Power dissipation; Very large scale integration; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
