Title :
A 3.3-V, 10-b, 25-MSample/s two-step ADC in 0.35-μm CMOS
Author :
Van der Ploeg, Hendrik ; Remmers, Robert
Author_Institution :
Philips Res. Lab., Eindhoven, Netherlands
fDate :
12/1/1999 12:00:00 AM
Abstract :
This paper describes the design of a two-step analog-to-digital converter (ADC). By using techniques such as improved switching and offset compensated amplifiers, the high-speed two-step architecture can be expanded toward high resolution. The ADC presented here achieves 9 ENOB with a spurious-free dynamic range of more than 72 dB, at a sample rate of 25 MSample/s. The ADC is realized in a 0.35-μm mainstream CMOS process without options such as double poly. It measures 0.66 mm 2 and dissipates 195 mW from a 3.3-V power supply
Keywords :
CMOS integrated circuits; analogue-digital conversion; high-speed integrated circuits; low-power electronics; 0.35 micron; 10 bit; 195 mW; 3.3 V; CMOS two-step analog-to-digital converter; high-speed architecture; offset compensation; switching amplifier; Analog-digital conversion; Bandwidth; CMOS integrated circuits; CMOS process; CMOS technology; Capacitors; Dynamic range; Integrated circuit measurements; Laboratories; Power measurement;
Journal_Title :
Solid-State Circuits, IEEE Journal of
