Title :
A 0.155-, 0.622-, and 2.488-Gb/s automatic bit-rate selecting clock and data recovery IC for bit-rate transparent SDH systems
Author :
Scheytt, J. Christoph ; Hanke, Gerhard ; Langmann, Ulrich
Author_Institution :
Lehrstuhl fur Elektron. Bauelemente, Ruhr-Univ., Bochum, Germany
fDate :
12/1/1999 12:00:00 AM
Abstract :
This paper presents a 0.155-, 0.622-, and 2.488-Gb/s automatic bit-rate selecting clock and data recovery circuit for transparent synchronous digital hierarchy (SDH) systems. The IC incorporates a clock and data recovery phase-locked loop (PLL), a bit-rate detection circuit, and a reference PLL. A bit-rate detection circuit detects the instantaneous bit rate and switches the clock and data recovery PLL. The circuit was designed in a 25-GHz fT Si-bipolar transistor array and dissipates 680 mW from -5 V supply voltage. Jitter performance is compliant with SDH/SONET specifications
Keywords :
SONET; bipolar integrated circuits; digital communication; elemental semiconductors; optical communication equipment; phase locked loops; silicon; synchronisation; synchronous digital hierarchy; timing; -5 V; 0.155 to 2.488 Gbit/s; 25 GHz; 680 mW; SDH/SONET specifications; Si; Si bipolar transistor array; automatic bit-rate selection; bit-rate detection circuit; bit-rate transparent SDH systems; clock recovery IC; data recovery IC; data recovery PLL; phase-locked loop; reference PLL; synchronous digital hierarchy systems; Bit rate; Clocks; Jitter; Phase detection; Phase locked loops; SONET; Switches; Switching circuits; Synchronous digital hierarchy; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
