• DocumentCode
    1278080
  • Title

    Evaluation of CVD/PVD multilayered seed for electrochemical deposition of Cu-damascene interconnects

  • Author

    Furuya, Akira ; Tagami, Masayoshi ; Shiba, Kazutoshi ; Kikuta, Kuniko ; Hayashi, Yoshihiro

  • Author_Institution
    NEC Corp., Kanagawa, Japan
  • Volume
    49
  • Issue
    5
  • fYear
    2002
  • fDate
    5/1/2002 12:00:00 AM
  • Firstpage
    733
  • Lastpage
    738
  • Abstract
    Multilayered seed for electrochemical deposition (ECD) of Cu was investigated to develop narrow-pitched, dual-damascene Cu interconnects that will be required for future ULSI devices. The seed was obtained by the physical vapor deposition (PVD) of a Cu film followed by the chemical vapor deposition (CVD) of a Cu film. The seed of the thinner CVD-Cu element and the thicker PVD-Cu element demonstrated better filling characteristics in high-aspect ratio vias. Good current-voltage characteristics were demonstrated using the multilayered seed technique with Cu dual-damascene interconnects (0.28 μm minimum via size) resulting in a via resistance about 0.7 Ω. In addition, ring-oscillator circuits were fabricated by integrating the double-layered interconnects with a transistor having a 0.18 μm gate width. The propagation delay per inverter, which had an interconnect with 104 vias, was about 6 ns. We successfully fabricated multilevel Cu-damascene interconnects, which are available for future high-speed devices using this multilayered seed technique
  • Keywords
    ULSI; copper; electrodeposition; integrated circuit interconnections; metallic thin films; Cu; Cu dual-damascene interconnect; Cu film; ULSI device; chemical vapor deposition; current-voltage characteristics; electrochemical deposition; high aspect ratio structure; high-speed device; multilayered seed; multilevel interconnect; physical vapor deposition; propagation delay; ring oscillator; via filling; via resistance; Adhesives; Atherosclerosis; Chemical elements; Chemical vapor deposition; Conducting materials; Delay; Electric resistance; Fabrication; Integrated circuit interconnections; Ultra large scale integration;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/16.998578
  • Filename
    998578