Damage generation and location in n- and p-MOSFETs biased in the Substrate-Enhanced Gate Current regime

This paper analyzes MOSFET degradation in the regime of hot carrier injection enhanced by substrate bias Substrate-Enhanced Gate Current (SEGC). The results are compared with the damage generated during conventional Channel Hot Carrier (CHC) stress experiments. The investigation was carried out on state of the art n⁺-poly n-MOSFETs and p⁺-poly p-MOSFETs, and it includes both a detailed characterization of standard electrical parameters (i.e., threshold voltage, drain current and linear transconductance) and a spatial profiling of stress-induced interface states. Our results reveal that the application of a substrate bias enhances degradation on both n-MOS and p-MOS devices and spreads toward the center of the channel the spatial profile of the damage. For a given gate current and oxide field in the injection region, the total amount of the generated damage is quite similar in both cases, but in the SEGC regime, the spatial distribution of generated traps is more distributed along the channel