Design methodology of the high performance large-grain polysilicon MOSFET

Author

Jagar, Singh ; Wang, Hongmei ; Chan, Mansun

Author_Institution

Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon, China

Volume

49

Issue

5

fYear

2002

fDate

5/1/2002 12:00:00 AM

Firstpage

795

Lastpage

801

Abstract

A methodology to design high-performance MOSFETs on the large-grain polysilicon-on-insulator (LPSOI) film is presented. Due to the metal-induced lateral crystallization (MILC) process in the formation of LPSOI films, the polysilicon grain locations and orientations can be reasonably controlled. Therefore, the performance of an LPSOI MOSFET can be optimized by carefully selecting the orientation and grain location according to the size of the desired transistor. The effects of various design parameters including the distance from the nickel strip, relative source/drain position, transistor orientation, and layout geometry are investigated. A ladder layout method is proposed to provide scalability in the design of high performance LPSOI MOSFETs. A design guideline for designing LPSOI NMOSFETs with different dimensions is given

Keywords

MOSFET; crystallisation; grain size; silicon-on-insulator; thin film transistors; LPSOI film; Si; design methodology; device scalability; ladder layout method; large-grain polysilicon MOSFET; metal-induced lateral crystallization; Active matrix liquid crystal displays; Crystallization; Design methodology; Grain size; Guidelines; MOSFET circuits; Nickel; Silicon; Strips; Thin film transistors;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.998586

Filename

998586