Property-based test generation for scan designs and the effects of the test application scheme and scan selection on the number of detectable faults

Scan circuits are considered under a test application scheme where a test consists of one or more primary input vectors embedded between a scan-in operation and a scan-out operation. The first property-based (simulation-based) test generation procedure under this test application scheme is described. The proposed procedure constructs tests that traverse as many pairs of fault-free/faulty states as possible. Additional techniques are incorporated into this basic procedure to enhance its effectiveness. Also considered for the first time is the set of detectable faults under this test application scheme. It is shown that it is a subset of the set of detectable faults obtained under the test application scheme where scan is applied with every primary input vector. It is also shown that the set of detectable faults depends strongly on the set of scanned flip-flops even when the percentage of scanned flip-flops is very high. This dependence at high levels of scan is significantly weaker when scan is applied with every primary input vector