A single chip digital satellite receiver with 6-bit A/D converter

This paper describes a single chip DVB/DSS compliant receiver that integrates a variable rate QPSK demodulator with a 6-bit A/D converter, a Viterbi decoder, a deinterleaver, and a Reed-Solomon decoder. Using a fixed rate-sampling clock it handles a continuously variable symbol rate from 1 Msps to 55 Msps with a 75 MHz clock. Careful floorplanning and flat placement and routing squeezed the 210,000 NAND-equivalent gate design into an area of 25 mm². It has been fabricated with a 0.35 μm CMOS TLM process, extensively tested in a real-world set-up and proves fully functional.