Title :
Clock-biased local bit line for high performance register files
Author :
Gong, Na ; Wang, Jiacheng ; Jiang, Siwei ; Sridhar, Rajeswari
Author_Institution :
State Univ. of New York at Buffalo, Buffalo, NY, USA
Abstract :
A clock-biased local bit line (CB-LBL) scheme is presented to achieve high access speed and energy efficient operation for register files. Simulation results in 32nm high-k/metal gate CMOS predictive technology show 49.5% read latency reduction and 39.4% power savings, with less than 5% impact on noise immunity and within 1% increase in area overhead. Additionally, CB-LBL can achieve 99.8% parametric yield compared to its original 47.6% (conventional LBL design), while being scalable.
Keywords :
CMOS integrated circuits; logic design; shift registers; CB-LBL scheme; area overhead; clock-biased local bit line scheme; conventional LBL design; energy efficient operation; high access speed; high performance register files; high-k/metal gate CMOS predictive technology; noise immunity; parametric yield; power savings; read latency reduction; size 32 nm;
Journal_Title :
Electronics Letters
DOI :
10.1049/el.2012.0039
