DocumentCode
1279252
Title
Two-ring systolic array network for artificial neural networks
Author
Amin, Hayder ; Curtis, K.M. ; Gill, B. R Hayes
Author_Institution
Sch. of Electr. & Electron. Eng., Nottingham Univ., UK
Volume
146
Issue
5
fYear
1999
fDate
10/1/1999 12:00:00 AM
Firstpage
225
Lastpage
230
Abstract
The paper describes an efficient and fast systolic architecture for the implementation of artificial neural networks. The proposed architecture, TORAN (two-in-one ring array network), combines two-ring systolic array networks to perform two sets of weight-data pair multiplication operations in parallel. This increases the hardware by 40% but reduces by 50% the number of cycles to perform the weighted sum calculation compared with a single systolic ring-array network
Keywords
neural chips; systolic arrays; TORAN; artificial neural networks; two-in-one ring array network; two-ring systolic array network; weight-data pair multiplication operations; weighted sum calculation;
fLanguage
English
Journal_Title
Circuits, Devices and Systems, IEE Proceedings -
Publisher
iet
ISSN
1350-2409
Type
jour
DOI
10.1049/ip-cds:19990534
Filename
809337
Link To Document