DocumentCode :
1279373
Title :
A planarized shallow-trench-isolation for GaAs devices fabrication using liquid phase chemical enhanced oxidation process
Author :
Wu, Jau-Yi ; Wang, Hwei-Heng ; Sze, Po-Wen ; Wang, Yeong-Her ; Houng, Mau-Phon
Author_Institution :
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Volume :
23
Issue :
5
fYear :
2002
fDate :
5/1/2002 12:00:00 AM
Firstpage :
237
Lastpage :
239
Abstract :
A new planarized trench isolation technique for GaAs devices fabrication by a liquid phase chemical-enhanced oxidation (LPCEO) method is proposed. The LPCEO-trench-isolation technique can be operated at low temperature with a simple and low-cost process. As compared with conventional mesa isolation, the LPCEO-trench-isolation can provide better planarity and isolation properties. Finally, GaAs MOSFETs fabricated with LPCEO-trench-isolation and selective oxidized gate both by the LPCEO method are demonstrated.
Keywords :
III-V semiconductors; MOSFET; electron mobility; gallium arsenide; isolation technology; microwave field effect transistors; oxidation; GaAs; MOSFETs; electron mobility; liquid phase chemical enhanced oxidation process; low-cost process; mesa isolation; microwave discrete device; planarity; planarized shallow-trench-isolation; selective oxidized gate; Chemical processes; Etching; Fabrication; Gallium arsenide; MESFET integrated circuits; MMICs; Microwave devices; Oxidation; Planarization; Temperature;
fLanguage :
English
Journal_Title :
Electron Device Letters, IEEE
Publisher :
ieee
ISSN :
0741-3106
Type :
jour
DOI :
10.1109/55.998862
Filename :
998862
Link To Document :
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