Title :
A Switching Sequence for Linear Gradient Error Compensation in the DAC Design
Author :
Kuo, Ko-Chi ; Wu, Chi-Wei
Author_Institution :
Dept. of Comput. Sci. & Eng., Nat. Sun Yat-sen Univ., Kaohsiung, Taiwan
Abstract :
A switching sequence is proposed to compensate for the linear gradient error in the current source array of current-steering digital-to-analog converter (DAC). A systematic method is established to obtain a switching sequence for both 1-D and 2-D current source arrays. The proposed switching sequence is also validated by the mathematical induction and exhibits a minimum variance of error. The proposed switching sequence is implemented into a 10-bit DAC. Simulation results show that the proposed switching sequence performs with a better integral nonlinearity (INL) and differential nonlinearity (DNL) compared to those of other switching sequences. The DAC is fabricated in a 1P6M 0.18-μm 1.8-V CMOS process and consumes less than 25 mW of power. The measured INL and DNL of the fabricated 10-b DAC are less than 0.62 and 0.41 LSB, respectively.
Keywords :
CMOS digital integrated circuits; digital-analogue conversion; error compensation; 1D current source array; 1P6M CMOS process; 2D current source array; DAC design; current-steering digital-analog converter; differential nonlinearity; integral nonlinearity; linear gradient error; linear gradient error compensation; mathematical induction; size 0.18 mum; switching sequence; voltage 1.8 V; word length 10 bit; Arrays; Error compensation; Microprocessors; Semiconductor device measurement; Solid state circuits; Switches; Digital-to-analog converter (DAC); segmentation architecture; switching sequence;
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
DOI :
10.1109/TCSII.2011.2158728
