Simulation of the variability in microelectronic capacitors having polycrystalline dielectrics

Author

Cousins, Jesse L. ; Kotecki, David E.

Author_Institution

Dept. of Electr. & Comput. Eng., Maine Univ., Orono, ME, USA

Volume

23

Issue

5

fYear

2002

fDate

5/1/2002 12:00:00 AM

Firstpage

267

Lastpage

269

Abstract

The scaling down of on-chip microelectronic capacitors presents a considerable challenge for future microelectronic devices. High-permittivity polycrystalline dielectrics such as Ta/sub 2/O/sub 5/, SrTiO/sub 3/ (STO), or (Ba, Sr)TiO/sub 3/ (BSTO), have been considered as a potential replacement for conventional amorphous SiO/sub 2/ and SiN/sub x/. The polycrystalline microstructure of these materials may lead to capacitor-to-capacitor variations in charge storage capacity and charge retention. In this letter, a Monte Carlo simulation is used to assess these variations. Results show that as the average crystalline grain size becomes greater than 1% of the capacitor size, variations of 10% in capacitance and between 3-150% in leakage should be expected.

Keywords

DRAM chips; Monte Carlo methods; capacitors; circuit simulation; dielectric thin films; grain size; integrated circuit modelling; Ba/sub x/Sr/sub 1-x/TiO/sub 3/; DRAM chips; Monte Carlo simulation; SrTiO/sub 3/; Ta/sub 2/O/sub 5/; capacitor size; capacitor-to-capacitor variations; charge retention; charge storage capacity; crystalline grain size; device modeling; microelectronic capacitors; polycrystalline dielectrics; Amorphous materials; Capacitors; Crystalline materials; Crystallization; Dielectrics; Grain size; Material storage; Microelectronics; Microstructure; Silicon compounds;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.998872

Filename

998872