Abstract :
Large-capacity ATM switches, with switching capacity in excess of 40 Gb/s or 100 Gb/s, are becoming an essential part of network growth. To realize such switches requires technology know-how as well as implementation trade-off considerations. This article provides a system-level exploration of large-capacity ATM switches in terms of switch fabric scalability, cell buffer management, buffer design trade-off, call processing capabilities, and future trends in switch design
Keywords :
VLSI; asynchronous transfer mode; buffer storage; delays; packet switching; user interfaces; VLSI; buffer design trade-off; call processing; cell buffer management; cost-effective nonblocking switching system; large capacity ATM switches; low cell loss; low cross-switch delay; policing functions; switch design; switch fabric scalability; system-level considerations; user interface; Asynchronous transfer mode; Bandwidth; Fabrics; Large Hadron Collider; Process design; Scalability; Switches; Telecommunication traffic;
