DocumentCode
1279564
Title
Realization of large capacity ATM switches
Author
Kou, Kuei Y.
Author_Institution
NEC America Inc., USA
Volume
37
Issue
12
fYear
1999
fDate
12/1/1999 12:00:00 AM
Firstpage
120
Lastpage
123
Abstract
Large-capacity ATM switches, with switching capacity in excess of 40 Gb/s or 100 Gb/s, are becoming an essential part of network growth. To realize such switches requires technology know-how as well as implementation trade-off considerations. This article provides a system-level exploration of large-capacity ATM switches in terms of switch fabric scalability, cell buffer management, buffer design trade-off, call processing capabilities, and future trends in switch design
Keywords
VLSI; asynchronous transfer mode; buffer storage; delays; packet switching; user interfaces; VLSI; buffer design trade-off; call processing; cell buffer management; cost-effective nonblocking switching system; large capacity ATM switches; low cell loss; low cross-switch delay; policing functions; switch design; switch fabric scalability; system-level considerations; user interface; Asynchronous transfer mode; Bandwidth; Fabrics; Large Hadron Collider; Process design; Scalability; Switches; Telecommunication traffic;
fLanguage
English
Journal_Title
Communications Magazine, IEEE
Publisher
ieee
ISSN
0163-6804
Type
jour
DOI
10.1109/35.809395
Filename
809395
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