High performance asynchronous FIR filter design in GaAs

Author

Montiel-Nelson, J.A. ; Nooshabadi, S.V.

Author_Institution

Centre for Appl. Microelectron., Univ. de Las Palmas de Gran Canaria, Spain

Volume

144

Issue

5

fYear

1997

fDate

10/1/1997 12:00:00 AM

Firstpage

289

Lastpage

296

Abstract

An asynchronous FIR architecture design using a mixed mode logic approach in GaAs technology is presented. Combining an asynchronous design style with static and dynamic logic proves to be very suitable for high speed and low power implementation of real time mobile computing applications. The authors introduce a novel clocked dynamic latched (CDL) logic in GaAs to implement the micropipeline latches required in the single phase signalling. The reliable implementation of an 11-tap FIR filter in terms of speed, area and power dissipation in GaAs MESFET 0.6 μm Vitesse technology is demonstrated. This ASIC system is fully operative across the full range of process spread variations and the temperature range of 0 to 100°C. It is robust against power supply variations of 15%

Keywords

FIR filters; III-V semiconductors; MESFET integrated circuits; application specific integrated circuits; digital filters; field effect logic circuits; gallium arsenide; integrated circuit design; logic design; 0 to 100 C; 0.6 micron; ASIC system; CDL logic; GaAs; GaAs MESFET Vitesse technology; asynchronous FIR architecture; asynchronous FIR filter design; clocked dynamic latched logic; dynamic logic; high performance filter design; high speed implementation; low power implementation; micropipeline latches; mixed mode logic; real time mobile computing applications; single phase signalling; static logic;

fLanguage

English

Journal_Title

Circuits, Devices and Systems, IEE Proceedings -

Publisher

iet

ISSN

1350-2409

Type

jour

DOI

10.1049/ip-cds:19971324

Filename

629479