Differential register bank design for self timed differential bipolar technology

A high performance differential bipolar datapath based on the ARM architecture has been designed using `micropipeline´ self-timed techniques. The datapath design included a full-custom 31×32 bit register bank. Traditional bipolar single-ended design techniques are not suited to implementing a RAM of this size on the target technology. This has led to the adoption of a fully differential circuit for the RAM cell here. The paper describes the challenges of designing such a differential register bank and the surrounding self-timed control. The data path has been fabricated by GEC Plessey Semiconductors and is fully operational. Results for the register bank are presented in terms of speed, power consumption and area