Abstract :
New dynamic, semistatic, and fully static single-clock CMOS latches and flipflops are proposed. By removing the speed and power bottlenecks of the original true-single-phase clocking (TSPC) and the existing differential latches and flipflops, both delays and power consumptions are considerably reduced. For the nondifferential dynamic, the differential dynamic, the semistatic, and the fully static flipflops, the best reduction factors are 1.3, 2.1, 2.2, and 2.4 for delays and 1.9, 3.5, 3.4, and 6.5 for power-delay products with an average activity ratio (0.25), respectively. The total and the clocked transistor numbers are decreased. In the new differential flipflops, clock loads are minimized and logic-related transistors are purely n-type in both n- and p-latches, giving additional speed advantage to this kind of CMOS circuits
Keywords :
CMOS logic circuits; circuit optimisation; clocks; delays; flip-flops; integrated circuit design; activity ratio; clock loads; delays; differential dynamic devices; flipflops; fully static devices; logic-related transistors; nondifferential dynamic devices; power consumptions; power-delay products; semistatic devices; single-clock CMOS latches; CMOS logic circuits; CMOS technology; Clocks; Delay; Digital circuits; Energy consumption; Frequency; Latches; Random access memory; Switches; Tin; Voltage;
