Title :
Charge injection error reduction circuit for switched-current systems
Author :
Riffaud, P. ; Tourneur, G. ; Garnier, E. ; Roux, P.
Author_Institution :
Lab. d´´Etudes de l´´Integration des Composants et Syst., Bordeaux I Univ., Talence, France
fDate :
9/25/1997 12:00:00 AM
Abstract :
The authors propose a novel circuit for reducing the charge injection error based on the technique of current source replication, applied to a second generation memory cell. Using the proposed circuit, offset error, linear gain error, and total harmonic distortion are significantly reduced to the detriment of the occupied die area and the power dissipation which are multiplied by a factor of three
Keywords :
CMOS analogue integrated circuits; electric charge; errors; harmonic distortion; switched current circuits; CMOS SI circuits; THD reduction; charge injection error reduction circuit; current source replication; die area; linear gain error; offset error; power dissipation; second generation memory cell; switched-current systems; total harmonic distortion;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19971172
