Title :
A high-performance two-stage packet switch architecture
Author :
Brown, Timothy X.
Author_Institution :
Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
fDate :
12/1/1999 12:00:00 AM
Abstract :
This paper contributes a distributed packet controller which reduces queueing to a single stage in two-stage packet switches. Software and neural network based controllers are described. Simulations under a range of traffic conditions for a 1024×1024 switch size shows the simplest architecture has the best performance
Keywords :
asynchronous transfer mode; buffer storage; controllers; distributed control; neural nets; packet switching; queueing theory; shared memory systems; telecommunication computing; telecommunication congestion control; ATM switch; distributed packet controller; high-performance switch architecture; neural network based controller; output-buffered shared memory switches; queueing reduction; simulations; software based controller; switch size; traffic conditions; two-stage packet switch architecture; Asynchronous transfer mode; Communication system traffic control; Computer architecture; Distributed control; Neural networks; Neurons; Packet switching; Switches; Throughput; Traffic control;
Journal_Title :
Communications, IEEE Transactions on
