Manufacturability of single and double-gate ultrathin silicon film fully depleted SOI technologies

Of several possible devices that can be used for sub-70 nm node technologies, two are built on ultra thin SOI layers. Scaling of such thin silicon layer SOI devices is constrained by the severe short channel control problem. To alleviate this, double-gate structures have been proposed by Wong et al. (1999), Chang et al. (2000), and Ieong et al. (2000). In this paper, we assess the manufacturability of single-gate (SG) and symmetric double-gate (DG) devices for gate lengths between 15 and 70 nm. Our results show that SG devices are not only manufacturable but also have tighter distributions than DG devices; inverter ring oscillator (RO) stage delays and power consumption are also better for SG devices. Besides gate length we find two additional major sources of variation: silicon thickness and encapsulation width. We show that for an optimized double-gate device with minimized parasitic resistance, CD variations become a dominant factor at 20-nm gate lengths despite superior electrostatic integrity. Also, the work function of metal gates must be controlled to better than ±0.1 eV (3σ) to avoid severe manufacturability problems