DocumentCode :
1280545
Title :
Stencil mask ion implantation technology
Author :
Shibata, Takeshi ; Suguro, Kyoichi ; Sugihara, Kazuyoshi ; Nishihashi, Tsutomu ; Fujiyama, Junki ; Sakurada, Yuzo
Author_Institution :
Process & Manuf. Eng. Center, Toshiba Corp., Yokohama, Japan
Volume :
15
Issue :
2
fYear :
2002
fDate :
5/1/2002 12:00:00 AM
Firstpage :
183
Lastpage :
188
Abstract :
The ion implantation process is important for the development or manufacturing of semiconductor devices, because ion implantation conditions directly influence some characteristics of semiconductor devices. Recently, we developed a new implantation technology, stencil mask ion implantation technology (SMIT). In the SMIT system, the stencil mask acts like a resist mask, and ions passing through the mask holes are implanted into selected regions of the Si substrate chip by chip. Use of SMIT has several advantages, notably lower manufacturing cost and shorter process time than in the case of conventional processing, because no photolithography process (including deposition and stripping of resist) is required. We have already demonstrated an application of SMIT to transistor fabrication, using various implanted dose conditions for the same wafer. Threshold voltage values can be controlled as effectively by implanted doses as they can by conventional implantation, and the dose dependence of the threshold voltage could be obtained from one wafer to which various implantation conditions are applied. Using SMIT, implantation conditions can be changed chip by chip without additional processes. This flexibility of implantation conditions is another advantage of SMIT. In this paper, we propose stencil mask ion implantation technology and show some fundamental results obtained by applying SMIT
Keywords :
MOSFET; doping profiles; integrated circuit economics; integrated circuit interconnections; integrated circuit metallisation; integrated circuit technology; ion implantation; masks; MOSFET; SMIT; SMIT system; Si; Si substrate; damascene metal gate; implantation condition flexibility; implantation technology; implanted dose conditions; implanted doses; ion implantation conditions; ion implantation process; manufacturing cost; mask holes; photolithography process; process time; resist mask; semiconductor device characteristics; semiconductor devices; stencil mask; stencil mask ion implantation technology; threshold voltage control; threshold voltage dose dependence; transistor fabrication; wafer implantation conditions; Costs; Fabrication; Ion implantation; Lithography; Manufacturing processes; Resists; Semiconductor device manufacture; Semiconductor devices; Substrates; Threshold voltage;
fLanguage :
English
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
Publisher :
ieee
ISSN :
0894-6507
Type :
jour
DOI :
10.1109/66.999589
Filename :
999589
Link To Document :
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