Title :
High yielding self-aligned contact process for a 0.150-μm DRAM technology
Author :
Dobuzinsky, D. ; Faltermeier, J. ; Gambino, J.
fDate :
5/1/2002 12:00:00 AM
Abstract :
This paper describes improvements in the self-aligned contact process for 0.150 μm and 0.175 μm technology generations. Using a dynamic random access memory cell layout, we show that self-aligned contacts can be formed at 0.175 μm ground rules and beyond by using a C4F8-CH2F2 chemistry. With the improved etch selectivity, gate cap nitride thickness can be reduced, resulting in a smaller aspect ratio for the gate etch, borophosphosilicate glass fill, and contact etch. With a rectangular contact, the area can be increased and the process windows for lithography and etch are improved. The process window for lithography increases by up to 40%, the aspect ratio for the etch and the contact fill is less, and the sensitivity to misalignment is reduced. The combination of rectangular contacts and C4F8-CH 2F2 chemistry greatly enhances the product yield
Keywords :
DRAM chips; electrical contacts; integrated circuit interconnections; integrated circuit metallisation; integrated circuit yield; lithography; plasma materials processing; sputter etching; 0.15 micron; 0.175 micron; B2O3-P2O5-SiO2; BPSG; DRAM technology; RIE; Si3N4; aspect ratio; borderless contact; borophosphosilicate glass fill; contact etch; contact fill; contact shape; dynamic random access memory cell layout; etch chemistry; etch process windows; etch selectivity; etch stop; gate cap nitride thickness; gate etch; ground rules; high yield self-aligned contact process; lithography process windows; misalignment sensitivity; product yield; reactive ion etching; rectangular contact; selective etching; self-aligned contact process; self-aligned contacts; technology generations; Chemical technology; Chemistry; Contacts; DRAM chips; Etching; Glass; Polymers; Random access memory; Silicon compounds; Windows;
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
