A 200 MHz register-based wave-pipelined 64 M synchronous DRAM

Author

Song, Ho-Jun ; Kim, Jung-Pill ; Lee, Jae-Jin ; Oh, Jong-Hoon ; Ahn, Seung-Han ; Hwang, Inseok

Author_Institution

Dept. of Electron. Eng., Chungnam Nat. Univ., Daejeon, South Korea

Volume

32

Issue

1

fYear

1997

fDate

1/1/1997 12:00:00 AM

Firstpage

92

Lastpage

99

Abstract

A new register-based wave-pipelined scheme for synchronous DRAMs (SDRAMs) is proposed. In this scheme, (N-1) registers are located between a read data bus line pair and a data output buffer and (N-1) read data are stored in parallel in these registers, where N denotes the CAS latency. Since the column data path is not divided and the read data is transmitted directly to the registers, the burst read operation can easily be achieved at a higher operation frequency without a large area penalty or degradation of an internal timing margin. Measured results show that the 64 M SDRAM based on the register-based wave-pipelined scheme can operate up to 200 MHz

Keywords

CMOS memory circuits; DRAM chips; pipeline processing; 200 MHz; 64 Mbit; CMOS technology; burst read operation; internal timing margin; operation frequency; register-based wave-pipelined scheme; synchronous DRAM; Buffer storage; Clocks; Content addressable storage; Decoding; Degradation; Delay; Frequency conversion; Random access memory; SDRAM; Timing;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.553186

Filename

553186