A new 3D-PICS High density Integrated Passive Device with substrate noise reduction by localized P+ guard rings: Characterization and modeling

This paper presents an original concept of a 3D-PICS High density Integrated Passive Device Technology with P+ guard rings realized in a 300μm depth High Resistivity Silicon Substrate (HRS) in order to reduce significantly the substrate noise coupling. In this paper, a 3D-PICS IPD test chip was studied as the passive part prototype of a System-In-Package chip in combination with RF transceiver operating in the ISM band (863-870 MHz). Various configurations of the passive chip layout (including implementation of guard rings) have been characterized by Direct Power Injection. 3D-PICS electrical performances deduced from two-ports S-parameters are reported, as well as the guard rings efficiency measurements and a compact high frequency model based on S-parameters extraction. Coupling isolation performances of the new integrated PICS components are found satisfactory.