• DocumentCode
    1280922
  • Title

    Low voltage CMOS full adder cells

  • Author

    Radhakrishnan, Radhakrishnan D.

  • Author_Institution
    Sch. of Appl. Sci., Nanyang Technol. Univ., Singapore
  • Volume
    35
  • Issue
    21
  • fYear
    1999
  • fDate
    10/14/1999 12:00:00 AM
  • Firstpage
    1792
  • Lastpage
    1794
  • Abstract
    A formal design procedure for realising a minimal transistor CMOS XOR-XNOR cell using pass networks is presented that successfully scales down with power supply voltage and fully compensates for the threshold voltage drop in MOS transistors. A full adder using this cell is also presented
  • Keywords
    CMOS logic circuits; adders; integrated circuit design; logic design; logic gates; low-power electronics; CMOS XOR-XNOR cell; LV CMOS full adder cells; formal design procedure; low voltage cells; minimal transistor CMOS cell; pass networks; power supply voltage; threshold voltage drop compensation;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19991282
  • Filename
    809971
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1280922